Hardware Interrupts

There are two types of hardware interrupt on the ARM, irq and fiq. fiq is an abbreviation of Fast Interrupt. The ARM has 2 interrupt lines entering it, one for each interrupt. An irq cannot interrupt a fiq. When an interrupt is signalled on one of these lines, the ARM switches into the corresponding privileged mode and will typically enter the kernel, indirected via 0x18 for irq and 0x1C for fiq. These modes also have their own private registers, R13_irq and R14_irq; and R8_fiq to R14_fiq. Again, R14 is set up by the processor to point to the appropriate return address once the interrupt has been handled.

Devices are multiplexed onto these two lines by the IO controller (IOC in old machines and IOMD in newer machines). In order to find out which device triggered the interrupt, it is necessary to read the status registers from IOC (which is memory mapped). The I/O map is illustrated in Figure 

Figure: Memory map of interrupt sources